Thin semiconductor chips are becoming increasingly important. On one hand, the semiconductor chip thickness has a direct influence on the overall height of the encapsulated semiconductor device, and on the other hand thin semiconductor chips have a higher mechanical flexibility or a certain flexural elasticity. The production of thin semiconductor chips is therefore necessary in order to realize very thin semiconductor devices as part of miniaturization and to produce elastic semiconductor modules which are used, e.g., in chip cards.
The term “thin” according to the described device refers to wafers and/or semiconductor chips with a thickness of ≦150 μm, and in particular wafers and/or semiconductor chips with a thickness of ≦100 μm.
The production of thin semiconductor chips requires new types of production and working processes. To minimize handling of thin semiconductor chips or wafers during production, a known method has been developed allowing thin semiconductor chips to be produced from the thick, unground wafers without thin wafers having to be handled during the course of the process. In semiconductor assembly, this method is known as “dicing before grinding” (DBG).
In this known method, a first step requires the thick wafer to be sawn into from its top surface, i.e., the surface including the semiconductor chip structures, according to the thickness of the finished semiconductor chip. In a subsequent step, the top surface of the wafer which has been prepared in this way is applied to a protective sheet and then thinned from the back surface until the semiconductor chips are present in singulated form.
Mounting of the thin semiconductor chips requires a joining material between the semiconductor chips and a substrate. Separate application of the semiconductor chip and the joining material to the substrate involves drawbacks. A first drawback is that at least two method steps, namely the application of the joining material and the application of the semiconductor chip, are required. A second drawback is that both joining material and semiconductor chip each must be aligned on the substrate, which in practice requires complex setting of a plurality of modules with respect to one another.
In the present text, the term “substrate” is to be understood as meaning supports to which semiconductor chips are applied and which represent the external contacts for the installation of the fully encapsulated semiconductor device. A substrate in the context of the present method may include various materials, such as, e.g., ceramic, metals or an organic plastics material.
Methods are known for applying an adhesive sheet to the back surface of the semiconductor wafer, which has been thinned and divided into semiconductor chips, to act as the joining material. This technique has the drawback of requiring an additional dividing step in order to divide the sheet on the back surface of the semiconductor wafer which has been divided into semiconductor chips into individual sheets for each semiconductor chip. This in particular presents the risk of the semiconductor chips being contaminated with the sheet material. Moreover, the singulation of the sheet on the back surface of the semiconductor wafer which has been divided into semiconductor chips requires an additional procedure to apply the sheet to the back surface of the thinned and divided semiconductor wafer.
Methods are also known in which an adhesive sheet is applied to the back surface of the unthinned semiconductor wafer, and the silicon material and the adhesive sheet made from joining material are singulated simultaneously with the introduction of the dividing gaps for the individual semiconductor chips. This method has a first drawback in that there is a risk of contamination to the semiconductor material with the joining material. The second disadvantage is that the dividing tool is required to cut through two different materials at the same time, which is detrimental to the tool costs and service life of the dividing tool. A further drawback to the methods of the known art is that structuring of joining material on the back surfaces of the semiconductor chips is not possible. Therefore, the area of the joining material in each case corresponds to the entire area of the surface of the semiconductor chips.